Volume 13 Issue 2 July-December 2024
| S.No | Title of The Paper | Page No | Download |
|---|---|---|---|
| 1 | Among the associated college students of King Fahd University in Hafr AL Batin: a cross-sectional study of body mass index, aerobic fitness, and dietary habits. Author(s): Abdul Rasoole AL Rahman, Rajab AL Rafati DOI : https://ijaep.2024.v13.i02.pp01-12 |
1-12 |  |
| 2 | The Effects of Working Out at the Same Time Effects of Exercise-Related Hypotension on Prehypertensive Men: A Modality-Based Approach Author(s): Hasinaa Rashwan Abdallahg DOI : https://ijaep.2024.v13.i02.pp13-19 |
13-19 | |
| 3 | Rehabilitating the Body and Movement Following Total Ankle Arthroplasty Author(s): Mohamed Kamal Aly Moussa DOI : https://ijaep.2024.v130.i02.pp20-39 |
20-39 | |
| 4 | Improving Explosive Power and Speed Following a Heavy Load Warm-Up: Post-Activation Potentiation Author(s): Dr / Mohamed Fekry Elmoghany DOI : https://ijaep.2024.v13.i02.pp40-50 |
40-50 | |
| 5 | COMPARATIVE ANALYSIS 4:1 MULTIPLEXER USING CMOS TECHNOLOGY NANOMETER REGIME Author(s): K VIJAYA SREE, E NIKITHA, B BHANU PRAKASH, Dr. M Krishna Chaitanya DOI : https://ijaep.2024.v13.i02.pp51-63 |
51- 63 | |
| 6 | Performance Analysis of 9Transistor SRAM Cell Using CMOS Author(s): P KAVERI, M GANESH, G BHANU PRASAD, Dr. M. Mahesh DOI : https://ijaep.2024.v13.i02.pp64-78 |
64-78 | |
| 7 | Design and Analysis Of 2x4 Decoder Using CMOS Technology Author(s): M SHIRISHA, B SATHYATEJA, G MANOJ, Dr. V. Vijaya Bhaskar, DOI : https://ijaep.2024.v13.i02.pp79-89 |
79-89 | |
| 8 | Design Of D-Flip-Flop Circuits Using TG Methodology Author(s): D NIKHIL, K VAISHNAVI, V BHANU KIRAN, Mrs. M. Sumalatha DOI : https://ijaep.2024.v13.i02.pp90-100 |
90-100 | |
| 9 | Performance Analysis Of Generic Full Adder Based On modified Technique Author(s): J USHA RANI, P NAVEEN. M NAVYASRI, Mrs. V. Sravanthi DOI : https://ijaep.2024.v13.i02.pp101-114 |
101-114 | |
| 10 | Design of High Performance of 2×4 Decoder Using 16 nm Technology. Author(s): M SHIRISHA, B SATHYATEJA, G MANOJ, Mrs. M. Sumalatha DOI : https://ijaep.2024.v13.i02.pp115-128 |
115-128 | |
| 11 | DESIGN AND VERIFICATION OF LOW POWER LOW AREA HIGH EFFICIENT 4 BIT COUNTER USING CMOS TECHNOLOGY Author(s): Mahesh Bolishetti, A Prutha Rani, D Shirisha DOI : https://ijaep.2024.v13.i02.pp129-144 |
129-144 | |
| 12 | DESIGN AND IMPLEMENTATION OF LOW POWER AREA EFFECTIVE HYBRID MODE 2×4 DECODER FOR MEMORY APPLICATIONS USING 16 NM TECHNOLOGY. Author(s): Pothuganti Sasya Reddy, V SRAVANTHI, Dr.V.Vijaya bhasker DOI : https://ijaep.2024.v13.i02.pp145-160 |
145-160 | |
| 13 | Design and implementation of low noise power low and high speed three stage comparator using 16nm Technology Author(s): P. Sahithi, D SHIRISHA, M.Kiranmayi DOI : https://ijaep.2024.v13.i02.pp161-170 |
161-170 | |
| 14 | Design and verification of high perormance and effective area 9T Transimssiion gate based SRAM using CMOS Technology Author(s): Mudam Banu Prasad, Dr.V.Vijaya bhasker, M.Sumalatha DOI : https://ijaep.2024.v13.i02.pp171-186 |
171-186 | |
| 15 | Design and implementation of low power high speed Pass Transistor based level shifter using CMOS Technology Author(s): Ramavath Linga, M.Sumalatha, M.Kiranmayi DOI : https://ijaep.2024.v13.i02.pp187-203 |
187-203 | |
| 16 | DESIGN AND VALIDATION OF LOW POWER AND HIGH EFFICIENT MUX BASED 4 BIT BARREL SHIFTER USING 32NM FINFET TECHNOLOGY Author(s): Gode Nagesh, Dr.M.Krishna chaitanya, Dr.V.Vijaya bhasker DOI : https://ijaep.2024.v13.i02.pp204-219 |
204-219 | |
| 17 | LOW POWER LOW AREA HIGH EFFICIENT HYBRID MODE FULL ADDER USING 16NM CMOS TECHNOLOGY Author(s): Pallepati Deepika, V SRAVANTHI, M.Sumalatha DOI : https://ijaep.2024.v13.i02.pp220-232 |
220-232 | |
| 18 | DESIGN AND IMPLEMENTATION OF HIGH SPEED LOW POWER MUX BASED FULL ADDER USING 16NM TECHNOLOGY Author(s): Kothapally Kanchana, Dr.V.Vijaya bhasker, D SHIRISHA DOI : https://ijaep.2024.v13.i02.pp233-248 |
233-248 | |
| 19 | DESIGN AND VERIFICATION OF HYBRID METHOD BASED N-BIT DIGITAL COMPARATOR USING 16NM CMOS TECHNOLOGY Author(s): RUDRA AMULYA, M.SUMALATHA, A PRUTHA RANI DOI : https://ijaep.2024.v13.i02.pp249-265 |
249-265 | |
| 20 | VERIFICATION AND VALIDATION OF HIGH EFFICIENT FAULT DIAGNOSIS FULL ADDER USING 16nm CMOS TECHNOLOGY Author(s): Alugoju Anil Kumar, Dr.M.Mahesh, V Sravanthi DOI : https://ijaep.2024.v13.i02.pp266-281 |
266-281 | |
| 21 | RFID READER AND NODE MCU SMART SHOPPING TROLLEY Author(s): M. Shruthi, D. SHIRISHA, M. Kiranmayi DOI : https://ijaep.2024.v13.i02.pp282-294 |
282-294 | |
| 22 | SMART WASTE SEGREGATION SYSTEM USING ARDUINO UNO Author(s): A.Sushmitha, Dr.V.Vijaya bhasker, D.SHIRISHA DOI : https://ijaep.2024.v13.i02.pp295-305 |
295-305 | |
| 23 | SMART AGRICULTURE MONITORING SYSTEM Author(s): CH BHAWANA, Dr.V.Vijaya bhasker, M.SUMALATHA DOI : https://ijaep.2024.v13.i02.pp306-313 |
306-313 | |
| 24 | DRIVER DROWSINESS DETECTION SYSTEM USING RASPBERRY PI Author(s): L.Pravalika, A.PRUTHA RANI, D.SHIRISHA DOI : https://ijaep.2024.v13.i02.pp314-322 |
314-322 | |
| 25 | HAND GESTURE CONTROLLED ROBOT USING ARDUINO Author(s): M.Swathi, M.SUMALATHA, A.PRUTHA RANI DOI : https://ijaep.2024.v13.i02.pp323-333 |
323-333 | |
| 26 | Methods for direct digital management of hybrid dynamic systems using inverse dynamics controllers and artificial neural network state estimators Author(s): Dr. N.V.Subba Rao, Dr. B. Ravi DOI : https://ijaep.2024.v13.i02.pp334-344 |
334-344 | |
| 27 | Locating Power Leaks and Preventing Power Outages in Residential Structures Author(s): Dr. N.V.Subba Rao, Dr. B. Ravi DOI : https://ijaep.2024.v13.i02.pp345-350 |
345-350 | |
| 28 | Locating and sizing reactive power compensation devices for voltage control ancillary services optimally using the HFPSO- TOPSIS technique Author(s): Dr. N.V.Subba Rao, Dr. B. Ravi DOI : https://ijaep.2024.v13.i02.pp351-362 |
351-362 | |
| 29 | CLOUD-BASED IMAGE ANALYSIS FOR AUTOMATED DETECTION OF FRUIT DISEASES Author(s): Mr.T Venkata Seshu Kiran , K.Akshara Reddy DOI : https://ijaep.2022.v11.i02.pp39-45 |
39-45 | |
| 30 | Formalization of Signalling System by Process Calculus Author(s): Nagam Aanjaneyulu, Lankala Mounika, Shaik Guntur Mahabub Subhani, Dr. Godagala Madhava Rao DOI : https://ijaep.2024.v13.i02.pp363-367 |
363-367 | |
| 31 | Framework and Architecture for Programming Education Environment as a Cloud Computing Service Author(s): Arekatla Madhava Reddy, Vanapamula Veerabrahmachari , Butukuru Rojalakshmi, Dr. Padigala Suresh DOI : https://ijaep.2024.v13.i02.pp368-374 |
368-374 | |
| 32 | Digital Control algorithm for Two-Stage DC-DC Converters Author(s): Lankala Mounika, Mr. Merugu Anand Kumar, Nagam Aanjaneyulu, Dr. Inaganti Shylaja DOI : https://ijaep.2024.v13.i02.pp375-379 |
375-379 | |